1. Technical Field
This disclosure relates to electronic circuits, and more particularly, to memory read latch circuits.
2. Description of the Related Art
Many integrated circuits (ICs) include memory circuits implemented thereon. For example, processors implemented on ICs often times include at least one cache memory, and typically include a set of registers.
On-chip memories may be implemented using circuits known as bit cells. Each bit cell may include transistors implementing a pair of cross-coupled inverters. Additional transistors may have gate terminals coupled to word lines, and may couple true and complementary nodes to corresponding true and complementary bit lines. As such, these types of bit cells may be implemented using six transistors, and may thus be known at 6T bit cells.
Some on-chip memories may be implemented with separate read and write ports. One mechanism for implementing such memories is to use eight transistor, or 8T bit cells. In an 8T bit cells, the true and complementary bit lines coupled to bit cells may be write bit lines, upon which data conveyed to a correspondingly coupled bit cell when a write word line is activated. Another transistor of the 8T bit cells includes a gate terminal coupled to one node of the bit cell's cross-coupled inverters, with yet another coupled in series and having a gate terminal coupled to a read word line. A read enable circuit may also be coupled to each bit cell or to groups of bit cells. When the read word line for a given bit cells is active and the read enable circuit enables coupling of the read line, a value stored in a corresponding bit cell may be conveyed to a read port.